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? ? 2011 nuvoton technology corporation WPCT301/npct501 trus ted platform module (t pm) version 1.2 with i 2 c interface www.nuvoton.com march 2011 revision 1.40 WPCT301/npct501 trusted platform module (tpm) version 1.2 with i 2 c interface general description the nuvoton WPCT301/npct501 family of single-chip trusted platform modules (tpm) is a third-generation nu- voton safekeeper ? device that implements the tcg ver- sion 1.2 specification for pc- client tpm with the addition of a serial data interface. the WPCT301/npct501 is de signed to reduce system power-up time and trusted os loading time. it provides a complete platform security solution for a wide range of com- puter systems. features general complete, single-chip tpm solution ? no external parts required compatible with the trusted computing group (tcg) tpm 1.2 main host interface ? tpm 1.2 interface (tis) emulation ? dedicated interrupt signal secure general-purpose i/o (gpio) ? up to three gpio pins ? i/o pins individually configured as input or output ? configurable internal pull-up resistors ? tcg 1.2-defined interface ? dedicated physical presence (pp) pin with config- urable pull-up or pull-down resistor tick counter bus interface i 2 c bus interface ? i 2 c slave ? up to 400 khz clock operation (npct501) clocking and supply on-chip clock generator power supply ? 3.3v supply operation ? separate pins for main (v dd ) and standby (v sb ) power supplies ? low standby power consumption package 28-pin thin shrink smal l outline package (tssop28) host i 2 c bus physical presence system block diagram WPCT301/ gpio npct501
www.nuvoton.com 2 revision 1.40 WPCT301/npct501 datasheet revision record revision date status comments february 2008 revision 0.9 preliminary datasheet march 2008 revision 1.0 preliminary datasheet, second release april 2008 revision 1.01 removed t wlb requirement fixed spi_do i/o definition in 1.3.1 serial interface fixed signal names in 3.4.3 i 2 c timing and 3.4.4 spi timing diagrams in 3.4.4 spi timing diagram, changed max frequency of t sck (spi timing) to 100 khz june 2008 revision 1.02 in 3.4.4 spi timing diagram, changed max frequency of t sck (spi timing) to 200 khz replaced figures 11 and 12 (page 20) november 2009 revision 1.03 nuvoton revision. changed logos and company name. january 2010 revision 1.04 order numbers changed (...0wg to ...0wx) added description to sadd pin august 2010 revision 1.05 changed power-well to v dd for all pins in section 1 (signal/pin connection and description). changed sadd description in section 1.3.3 . changed section 1.4 (internal pull-up and pull-down resistors). changed section 4.4.2 (reset timing). updated ta b l e 1 (?buffer types?) and updated section 1.3 (?signal/pin description?) tables, accordingly. december 2010 revision 1.10 removed references to the nuvoton wpct300 (spi interface). added the npct501 device. january 2011 revision 1.20 typo fixes. added tpm host interface description ( section 3 ). march 2011 revision 1.30 changed t srst max requirement from 2.5 s to none, in power-up reset timing table ( section 4.4.2 ). added t rst.sta to i 2 c timing table ( section 4.4.3 ). march 2011 revision 1.40 added npct501ma0wx orde r number to pinout diagram and back cover.
3 www.nuvoton.com revision 1.40 WPCT301/npct501 table of contents 1.0 signal/pin connection and description 1.1 connection diagram ........................................................................................................... 4 1.2 buffer types and signal/pin directory ...................................................................... 4 1.3 signal/pin descriptions .................................................................................................... .5 1.3.1 serial interface ......................................................................................................... ..... 5 1.3.2 inputs and outputs ...................................................................................................... .5 1.3.3 configuration straps and testing .................................................................................. 5 1.3.4 power and ground ........................................................................................................ 5 1.3.5 reserved ................................................................................................................. ...... 6 1.4 internal pull-up and pull-down resistors .............................................................. 6 2.0 trusted platform module (tpm) overview 2.1 system connections . ................................ ................. ................................ ............. .......... .7 2.2 power management (pm) .................................................................................................... 7 2.3 host interface ............................................................................................................. ........ 7 2.4 reset ......... ................. ............................................................................................ ................... 7 3.0 tpm host interface 3.1 serial tpm interface protocol (tsip) ......................................................................... 8 3.1.1 state machine, flow and timeouts .......... ..................................................................... 8 3.1.2 tis register mapping .................................................................................................... 9 4.0 device specifications 4.1 general dc electrical characteristics ................................................................. 10 4.1.1 recommended operating conditions ......................................................................... 10 4.1.2 absolute maximum ratings ......................................................................................... 10 4.1.3 capacitance ............................................................................................................. ... 10 4.1.4 power consumption unde r recommended operating condit ions .............................. 11 4.2 dc characteristics of pi ns by i/o buffer types ......... ................. ................ ......... 12 4.2.1 input, ttl compatible, with schmitt trig ger ............................................................... 12 4.2.2 input, reset pin ......................................................................................................... .. 12 4.2.3 output, ttl/cmos compatib le, push-pull buffer ...................................................... 12 4.2.4 output, open drain buffer ........................................................................................... 13 4.2.5 notes and exceptions .................................................................................................. 13 4.3 internal resistors ......................................................................................................... .. 14 4.3.1 pull-up resistor ......................................................................................................... .. 15 4.3.2 pull-down resistor ...................................................................................................... 1 5 4.4 ac electrical characteristics .................................................................................... 16 4.4.1 ac test conditions ................................................................................................... 1 6 4.4.2 reset timing ............................................................................................................. .. 17 power-up reset ................................................................................................... 17 4.4.3 i 2 c timing .................................................................................................................... 18 4.5 package thermal information ..................................................................................... 20
www.nuvoton.com 4 revision 1.40 WPCT301/npct501 1.0 signal/pin connect ion and description 1.1 connection diagram 1.2 buffer types and signal/pin directory the signal dc characteristics of the pins described in section 1.3 on page 5 are denoted by buffer type symbols, which are defined in table 1 . table 1. buffer types symbol description in ts input, ttl compatible, wi th 250 mv schmitt trigger in rst input, reset pin o p/n output, ttl/cmos compatible, push -pull buffer capable of sourcing p ma and sinking n ma od n output, ttl/cmos compatible, open-drain buffer capable of sinking n ma pwr power pin gnd ground pin 28-pin thin shrink small outl ine package (tssop28), jedec order numbers: WPCT301aa0wx npct501aa0wx npct501ma0wx nc reserved 15 16 17 18 19 20 21 22 23 24 25 26 27 28 28-pin (top view) WPCT301/ npct501 sint /gpio4 nc vss vdd nc nc reserved nc vdd vss nc sr eset 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tssop sclk xor_out/sdat nc nc vss vsb gpio2 pp test gpio3/sadd nc nc nc nc nc = not connected
1.0 signal/pin connect ion and description (continued) revision 1.40 5 www.nuvoton.com WPCT301/npct501 1.3 signal/pin descriptions this section describes all signals of the WPCT301/npct501 device. the signa ls are organized by functional group. 1.3.1 serial interface 1.3.2 inputs and outputs 1.3.3 configuration straps and testing 1.3.4 power and ground signal pin(s) i/o buffer type power well description sdat 1 i/o in ts /od 4 v dd serial data in/out. i 2 c data in/out. sclk 2 i/o in ts /od 4 v dd serial clock. i 2 c clock. sint 15 i/o in ts /od 8 , o 4/8 v dd serial communication command completion interrupt. active low as long as there is data on the output data fifo. sreset 16 i in rst v dd serial reset. host system reset used for the serial bus (hardware reset). signal pin(s) i/o buffer type power well description pp 7 i in ts v dd physical presence input. indicates owner?s physical presence. gpio4-2 15, 9, 6 i/o in ts /od 8 , o 4/8 v dd general-purpose i/o port. general-purpose i/o pins compatible with the pc client tpm 1.2 specification . signal pin(s) i/o buffer type power well description test 8 i in ts v dd test mode. sampled at v dd power-up reset to force the device pins into a xor tree or tri-state ? ? serial slave address. sampled at v dd power-up rese t to select the slave address, as follows: - no pull-down resistor - aeh (write) and afh (read) - 10 k ?? test mode selection. test mode (xor tree or tri-state) is selected by the sampled state of the sadd pin during vdd power-up reset. when sadd is sampled high, xor tree mode is selected. when sadd is sampled low, tri-state mode is selected, floating all output pins. xor_out 1 o o 4/8 v dd xor tree output. this pin is the output of the xor tree test logic. signal pin(s) i/o buffer type power well description vss 4, 18, 25 ignd ground. ground connection for both core logic and i/o buffers, for the main, standby and battery power supplies. vdd 19, 24 i pwr main 3.3v power supply. powers the i/o buffers of the gpio ports and the serial interface. vsb 5 i pwr standby 3.3v power supply. powers the on-chip core.
1.0 signal/pin connect ion and description (continued) www.nuvoton.com 6 revision 1.40 WPCT301/npct501 1.3.5 reserved 1.4 internal pull-up and pull-down resistors the signals listed in ta b l e 2 have internal pull-up (pu) and/or pull-down (pd) resistors. the internal resistors are optional for those signals indicated as ?programmable? signal pin(s) description nc 3, 10-14, 17, 20, 22-23, 26-27 not connected. these pins must be left unconnected. reserved 21, 28 reserved. these pins must be connected to an external 10 k ? table 2. WPCT301/npct501 internal pull-up and pull-down resistors signal pin(s) power well type comments WPCT301 npct501 sint /gpio4 15 v dd pu 66 pu 110 gpio4 programmable 1 1. controlled by tpm. default at reset: gpio4 disabled. gpio3-2 9, 6 v dd pu 66 pu 110 programmable pp 7v dd pu 66 /pd 50 pu 110 /pd 110 programmable 2 2. controlled by tpm. default at reset: pull-down enabled. test 8v dd pd 50 pd 110 strap sadd 9v dd pu 66 pu 110 strap sdat 1v dd pu 66 pu 110
7 www.nuvoton.com revision 1.40 WPCT301/npct501 2.0 trusted platform module (tpm) overview the WPCT301/npct501 provides tpm functionality in tcg 1.2-compliant systems and is designed to best meet the re- quirements of embedded computer systems. 2.1 system connections figure 1 shows the system connections of the WPCT301/npct501 in a typical system. tpm functions are all integrated on-chip. the majo r elements of the WPCT301/ npct501 interface are: host interface based on an i 2 c bus, with interrupt request. a physical presence input signal (pp) to indicate owner physical presence. gpio signals (gpio4-2), operated by tcg commands. 2.2 power management (pm) the WPCT301/npct501 has an advanced power mana gement scheme. the wake-up scheme enables the WPCT301/npct501 to respond to any kind of event that may r equire its attention. power consumption is minimized by dy- namically adjusting the internal power modes to the activi ty required by the host comm ands and other operations. the security functions (core and associated peripherals) are supplied by v sb power, which should be connected to the sys- tem standby power source (if standby power exists). if th e system does not have a standby power source, use the system main power source instead (i.e., connect the system main power source to the vsb pin). 2.3 host interface the host bus interface is based on a seri al interface. this interface fully emul ates the tis registers (as defined in the tcg pc client-specific specification . 2.4 reset serial reset performs the following actions: resets host interface state machine. resets the tpm interface host-controlled registers. figure 1. WPCT301/np ct501 system connection diagrams host system (i2c) gpio4-2 WPCT301/ npct501 gpio 3.3v system main power 3.3v system standby power vdd vsb pp physical presence sdat sreset sclk sint
www.nuvoton.com 8 revision 1.40 WPCT301/npct501 3.0 tpm host interface this chapter describes the tp m 1.2-compliant host interface. 3.1 serial tpm interface protocol (tsip) the WPCT301/npct501 tsip implement s the tis register set accessible through the serial bus (i 2 c). the protocol state ma- chine and register layout are implemented as defined in the tis specification . this section describes the state machine, send- ing commands to the tpm, reading results from the tpm, er ror handling, register mapping and communication sequences on the bus. 3.1.1 state machine, flow and timeouts the state machine follows the definition in sect ion 11.3.11 (?s tatus register?) in the tis specification . use the sequence defined in tcg pc client specific, device driver design principles, for tcg version 1.2 , to send or receive command input/output parameters. the tpm triggers sint interrupt on the transition to command completion state. the sint is an active-low signal, i.e., it goes low whenever tpm_sts.dataavail is set (and tpm_sts.valid is set), and goes back high when tpm_sts.dataavail is cleared. there are two methods for the host device driver to wait for the command execution to finish: interrupt (recommended) - sint signal assertion (i.e., transition from high to low) triggers an interrupt in the host in- terrupt controller, followed by the host issuing the interrupt handler code. polling - host device driver performs status polling by reading tpm_sts register to check if dataavail bit is set by tpm. in this method, it is recommended to add a delay between the consecutive reads of tpm_sts register. table 3 shows the recommended values for delays: when an error occurs (i.e., a timeout is reached) while in command reception or execution states, abort the command at any point by setting tpm_sts.commandready . after which the command can be resent. when an error occurs (timeout is reached) while in command completion state, set tpm_sts.responseretry , this causes the nuvoton tpm to restar t sending command output parameters. the effects of setting tpm_sts.commandready in the different tpm communication states are as follows: in ready state: ignored - stay in ready state in idle state: enter ready state, within timeout_b in command reception state: this is an abort . ? the tpm write fifo is cleared ? tpm enters idle state ? command can be resent in command completion state: this is an abort ? the tpm read and write fifo are cleared ? enter idle state in command execution state: this is an abort ? tpm aborts current command execution ? the tpm read and write fifo are cleared ? enter idle state table 3. delay between consecutive tpm_sts regi ster reads during command execution state duration since tpm_sts.tpmgo set recommended delay between consecutive tpm_sts reads 0 - 10 msec 2 msec more than 10 msec 10 msec
3.0 tpm host interface (continued) revision 1.40 9 www.nuvoton.com WPCT301/npct501 3.1.2 tis register mapping table 4 shows the tis register offs et mapping in the tsip space: any tis register writing or reading data is processed and tpm_sts register updated (including burstcount field) on an i 2 c stop condition. any part of a command?s input parameter write operation to tpm_wr_fifo should start at offset 20h. any part of a command?s output parameter read operation to tpm_rd_fifo should start at offset 40h. table 4. tis register offs et mapping in tsip space offset register name 1 1. for a detailed description of these registers, see the tis specification. r/w page size (bytes) description 00h tpm_sts r/w 2 2. offset 0 is r/w while of fset 1 (burstcount) is ro. 2 status register. provides tis status. 20h tpm_wr_fifo wo 32 write this register to send i nput command parameters during command reception state. 40h tpm_rd_fifo ro 32 read this register to receive out put command parameters during command completion state. 60h tpm_did_vid_rid ro 4 vendor, device and revision id: - WPCT301: 00fe1050h - npct501: 47fe1050h
www.nuvoton.com 10 revision 1.40 WPCT301/npct501 4.0 device specifications 4.1 general dc electrical characteristics 4.1.1 recommended operating conditions 4.1.2 absolute maximum ratings absolute maximum ratings are values beyond which damage to the device may occur. unless ot herwise specified, all volt- ages are relative to ground (v ss ). 4.1.3 capacitance symbol parameter min typ max unit v dd main 3v supply voltage 3.0 3.3 3.6 v v sb standby 3v supply voltage 3.0 3.3 3.6 v t a operating temperature 0 +70 ?c symbol parameter conditions min max unit v sup supply voltage 1 1. v sup is v dd , v sb . -0.3 +4.1 v v i input voltage -0.3 v dd + 0.5 v v o output voltage -0.3 v dd + 0.5 v t stg storage temperature -65 +165 ?c p d power dissipation 1w t l lead temperature soldering (10 s) +260 ?c esd tolerance c zap = 100 pf r zap = 1.5 k ? 2 2. value based on test complying with ra i-5-048-ra human body model esd testing. 2000 v symbol parameter conditions min typ 1 1. t a = 25 ? c; f = 1 mhz. max unit c in input pin capacitance 4 5 pf c io i/o pin capacitance 8 10 pf c o output pin capacitance 6 8 pf
4.0 device specifications (continued) revision 1.40 11 www.nuvoton.com WPCT301/npct501 4.1.4 power consumption under recommended operating conditions symbol parameter conditions 1 1. all parameters specified for 0 ? ? ? ? ? typ max unit i dd v dd average supply current v il = 0.5v, v ih = 2.4v, no load 510ma i sb v sb average supply current v il = 0.5v, v ih = 2.4v, no load 20 50 ma i sblp v sb quiescent supply current in idle mode 2 2. device is not performing any operation; no serial bus activity. v il = v ss , v ih = v sb , no load 300 700 ?
4.0 device specifications (continued) www.nuvoton.com 12 revision 1.40 WPCT301/npct501 4.2 dc characteristics of pins by i/o buffer types the tables in this section summarize the dc ch aracteristics of all device pins described in chapter 1.2 on page 4 . the char- acteristics describe the general i/o buffer types defined in table 1 on page 4 . 4.2.1 input, ttl compatible, with schmitt trigger symbol: in ts 4.2.2 input, reset pin symbol: in rst 4.2.3 output, ttl/cmos compatible, push-pull buffer symbol: o p/n output, ttl/cmos compatible, rail-to-rail push-pull buffer that is capable of sourcing p ma and sinking n ma. symbol parameter conditions min max unit v ih input high voltage 2 v sup 1 +0.5 1. v sup is v dd or v sb according to the power well of the input. v v il input low voltage ? ? ? ? ? symbol parameter conditions min max unit v ih input high voltage 0.5 v dd v dd +0.5 v v il input low voltage ? ? ? ? ? symbol parameter conditions min max unit v oh output high voltage i oh = ? p ma 2.4 v i oh = ? ? ?? n ma 0.4 v i ol = 50 ? ? ? ? ?
4.0 device specifications (continued) revision 1.40 13 www.nuvoton.com WPCT301/npct501 4.2.4 output, open drain buffer symbol: od n output, open drain capable of sinking n ma. 4.2.5 notes and exceptions 1. i ilk and i olk are measured in the following cases (where applicable): ? internal pull-up or pull-down resistor is disabled ? push-pull output buffer is disabled (tri-state mode) ? open-drain output buffer is at high level 2. some pins have an internal static pull-up resistor (when enabled) and therefore ma y have leakage current from v sup (when v in = 0). see section 1.4 on page 6 for a list of the relevant pins. 3. some pins have an internal static pu ll-down resistor (when enabled) and ther efore may have leakage current to gnd (when v in = v sup ). see section 1.4 on page 6 for a list of the relevant pins. 4. the following strap pins have an internal static pull- up resistor enabled during power-up reset and therefore may have leakage current from v sb (when v in = 0): sadd, test . 5. i oh is valid for a gpio pin only when it is not configured as open-drain. 6. in xor tree mode, the buffer type of the input pins included in the xor tree is in t (input, ttl compatible), regardless of the buffer type of these pins in normal device operation mode. symbol parameter conditions min max unit v ol output low voltage i ol = n ma 0.4 v i ol = 50 ? ? ?
4.0 device specifications (continued) www.nuvoton.com 14 revision 1.40 WPCT301/npct501 4.3 internal resistors dc test conditions notes : 1. v sup is v dd or v sb , according to the pin power well. 2. the equivalent resistance of the pull-up resistor is calculated by r pu = (v sup ? pull-up resistor test circuit pull-down resistor test circuit v sup pin a i pu v v pin device under te s t r pd v sup pin a i pd v v pin v sup figure 2. internal resistor test conditions, t a = 0 ? c to 70 ?c, v sup = 3.3v device under te s t r pu internal pull-up strap internal pull-down strap v sup pin a i pu v v pin device under te s t r pd v sup pin a i pd v v pin v sup device under te s t r pu v sup pin a i pu v v pin device under te s t r pd v sup pin a i pd v v pin v sup (v pin < v il ) strap sampled ?high? v sup 10 k ? ? ? ? (v pin < v il )( v pin > v ih ) 10 ? ? figure 3. internal resistor design requirements, t a = 0 ?c to 70 ? c, v sup = 3.3 v (v pin > v ih ) strap sampled ?low? strap sampled ?low? strap sampled ?high?
4.0 device specifications (continued) revision 1.40 15 www.nuvoton.com WPCT301/npct501 4.3.1 pull-up resistor symbol: pu nn 4.3.2 pull-down resistor symbol: pd nn symbol parameter conditions 1 1. ta = 0 ? ? min 2 2. not tested; guaranteed by characterization. typical max 2 unit r pu pull-up equivalent resistance v pin = 0v nn ?? nn nn + 66% k ? symbol parameter conditions 1 1. ta = 0 ? ? min 2 2. not tested; guaranteed by characterization. typical max 2 unit r pd pull-down equivalent resistance v pin = v sup nn ?? nn nn + 120% k ?
4.0 device specifications (continued) www.nuvoton.com 16 revision 1.40 WPCT301/npct501 4.4 ac electrical characteristics 4.4.1 ac test conditions figure 4. ac test conditions, t a = 0 ? c to 70 ?c, v sup = 3.0v - 3.6v notes : 1. v sup is v dd or v sb according to the power well of the pin. 2. c l = 50 pf for all output pins except the following pin gr oups (values include both jig and oscilloscope capacitance): s 1 = open ? ? ? ??? definitions the timing specifications in this section are relative to v il or v ih (according to the specific buffer type) on the rising or falling edges of all the signals, as shown in the followin g figures (unless specifically stated otherwise). figure 5. input setup and hold time figure 6. clock-to-output and propagation delay device under te s t 0.1 ? load circuit ac testing input, output waveform v sup v oh v ol v ih v il te s t p o i n t s v ih v il (notes 1, 2, 3) t h clock input v ih v il v ih v il t su v ih v il input s etup time input h old time t val t oh clock or output v ih v il v ih v il v ih v il input output h old time output v alid time
4.0 device specifications (continued) revision 1.40 17 www.nuvoton.com WPCT301/npct501 4.4.2 reset timing power-up reset figure 7. power-up reset symbol description reference conditions min 1 1. not tested; guaranteed by design. max 2 2. not tested; guaranteed by design. t sb2dd time between standby and main supply voltage before end of reset 0 ms t srst sreset active time v dd power-up to end of sreset 10 ms t plv strap valid time before end of reset 10 ms t eplv external strap pull-down resistor, valid time before end of reset 10 ms straps t plv v dd (power) sr eset v ddmin t srst v sb (power) v sbmin t sb2dd
4.0 device specifications (continued) www.nuvoton.com 18 revision 1.40 WPCT301/npct501 4.4.3 i 2 c timing symbol description min max units wpct 301 npct 501 wpct 301 npct 501 f scl clock frequency, scl 50 50 100 1 1. test conditions: r l = 1 k ? ? ? ? ? ? ? ? ? ? ? figure 8. bus timing
4.0 device specifications (continued) revision 1.40 19 www.nuvoton.com WPCT301/npct501 sdat figure 9. cycle, start, stop and acknowledge timing sclk stop condition start condition t wr word n bit 8 ack note: write/read cycle time (t wr ) = the time from a valid write/read sequence stop condition until the end of an internal operation. bit 9
4.0 device specifications (continued) www.nuvoton.com 20 revision 1.40 WPCT301/npct501 4.5 package thermal information thermal resistance (degrees c/w) theta jc and theta ja values for the WPCT301/npct501 packages are as follows: table 5. theta ( ? ) j values note: airflow for theta ja values is measured in linear feet per minute (lfpm). package type theta ja @0 lfpm theta ja @150 lfpm theta ja @250 lfpm theta ja @500 lfpm theta jc t s s o p 2 82 92 72 52 31 0
WPCT301/npct501 trusted platform module (tpm) version 1.2 with i 2 c interface www.nuvoton.com physical dimensions all dimensions are in millimeters. important notice nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, tr affic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore, nu- voton products are not intended for applications wherein failure of nuvoton products could result or lead to a situation wherei n personal injury, death or severe property or environmental damage could occur. nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indem nify nuvoton for any damages resulting from such improper use or sales. please note that all data and specifications are subject to change without notice. all trademarks of products and companies mentioned in this document belong to their respective owners. headquarters no. 4, creation rd. 3, science-based industrial park, hsinchu, taiwan, r.o.c tel: 886-3-5770066 fax: 886-3-5665577 http://www.nuvoton.com.tw (chinese) http://www.nuvoton.com (english) nuvoton technology corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-544-1718 fax: 1-408-544-1787 nuvoton technology (shanghai) ltd. 27f, 2299 yan an w. rd. shanghai, 200336 china tel: 86-21-62365999 fax: 86-21-62365998 taipei office 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c. tel: 886-2-2658-8066 fax: 886-2-8751-3579 winbond electronics corporation japan no. 2 ueno-bldg., 7-18, 3-chome shinyokohama kohoku-ku, yokohama, 222-0033 tel: 81-45-4781881 fax: 81-45-4781800 nuvoton technology (h.k.) ltd. unit 9-15, 22f, millennium city 2, 378 kwun tong rd., kowloon, hong kong tel: 852-27513100 fax: 852-27552064 for advanced pc product line information contact: apc.support@nuvoton.com ? ? 28-pin thin shrink small outline package (tssop28), jedec order numbers: WPCT301aa0wx npct501aa0wx npct501ma0wx

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